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cat-5 receiver with adjustable line equalization AD8128 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features tuned to compensate for category-5 (cat-5) cable losses up to 100 meters @ 120 mhz 2 voltage-controlled frequency response adjustment pins high frequency peaking adjustment broadband gain adjustment 2700 v/s slew rate low output noise 1.5 mv rms integrated noise (1 ghz) @ 100 meters equalized bandwidth dc output offset adjust low offset voltage error: 7 mv typ equalized pass-band ripple 1 db to 70 mhz input: differential or single ended supply current: 24 ma on 5 v small 8-lead 3 mm 3 mm lfcsp applications keyboard-video-mouse (kvm) rgb video over unshielded twisted pair (utp) cable receivers professional video projection and distribution security video functional block diagram v offset v gain v peak v out v in+ v in? AD8128 05699-001 hpf hpf lpf figure 1. general description the AD8128 is a high speed, differential receiver/equalizer that compensates for the transmission losses of unshielded twisted pair (utp) cat-5 cables. various frequency dependent gain stages are summed together to best approximate the inverse frequency response of cat-5/cat-5e cable. an equalized bandwidth of 120 mhz can be achieved for 100 meters of cable. the AD8128 can be used as a standalone receiver/equalizer or in conjunction with the ad8143, triple differential receiver, to provide a complete low cost solution for receiving rgb over utp cable in such applications as kvm. the AD8128 has three control pins for optimal cat-5/cat-5e compensation. the equalized cable length is directly proportional to the voltage applied to the v peak pin, which controls the amount of high frequency peaking. v gain adjusts the broadband gain from 0 db to 3 db, compensating for the resistive cable loss. v offset allows the output to be shifted by 2.5 v, adding flexibility for dc-coupled systems. low integrated output noise and offset voltage adjust make the AD8128 an excellent choice for dc-coupled wideband rgb- over-cat-5 applications. for systems where the utp cable is longer than 100 meters, two AD8128s can be cascaded to compensate for up to 200 meters of cat-5/cat-5e. the AD8128 is available in a 3 mm 3 mm 8-lead lfcsp and is rated to operate over the extended temperature range of ?40c to +85c.
AD8128 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 test circ u it .................................................................................... 8 theory of operation .........................................................................9 input common-mode voltage range considerations ............9 applications ..................................................................................... 10 kvm applications ..................................................................... 10 dc control pins ......................................................................... 10 cascaded applications ............................................................... 11 exposed pad (ep) ....................................................................... 11 layout and power supply decoupling considerations ......... 11 evaluation boards ...................................................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 10/05revision 0: initial version
AD8128 rev. 0 | page 3 of 12 specifications t a = 25c, v s = 5 v, r l = 150 , belden cable, v offset = 0 v, v gain and v peak set to optimized settings (see figure 4 ), unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance C3 db large signal bandwidth v out = 2 v p-p, 100 meter cat-5 120 mhz 1 db equalized bandwidth flatness v out = 2 v p-p 70 mhz rise/fall time v out = 2 v step, 50 meter cat-5 2 ns rise/fall time v out = 2 v step, 100 meter cat-5 3.6 ns settling time to 2% v out = 2 v step, 50 meter cat-5 26 ns settling time to 2% v out = 2 v step, 100 meter cat-5 36.4 ns integrated output voltage noise v peak = 0.9 v, v gain = 225 mv, bw = 1 ghz 1.5 mv rms dc performance input bias current 15.5 24 a v offset pin current 1.7 8.2 a v gain pin current 2 3.4 a v peak pin current 4.2 6.8 a input characteristics input differential voltage 2.8 v input common-mode voltage 3.0 v input resistance common mode 380 k differential 675 k input capacitance 1.7 pf common-mode rejection ratio (cmrr) 200 khz, v out /v in, cm ?63 ?74 db adjustment pins v peak input voltage relative to ground 0 1 v maximum peak gain @ 120 mhz, v peak = 1 v 20 db v gain input relative to ground 0 1 v maximum broadband gain v gain = 1 v 3 db v offset input range relative to ground 2.5 v v offset to v out gain 1 v/v output characteristics output voltage swing ?2.55 +2.7 v output offset voltage v offset = 0 v, rto ?10.9 +7 +18.7 mv output offset voltage drift ?5.5 v/c short-circuit output current 100 ma power supply operating voltage range 4.5 5.5 v quiescent supply current, i cc /i ee @ 5 v +24/?21 +31/?27 ma supply current drift, i cc /i ee +86/?77 a/c +power supply rejection ratio (psrr) rto ?48 ?59 db ?power supply rejection ratio (psrr) rto ?48 ?61 db temperature range ?40 +85 c
AD8128 rev. 0 | page 4 of 12 absolute maximum ratings table 2. parameter rating supply voltage 5.5 v input voltage v s v peak and v gain control pins ?3 v to +v s v offset control pins v s operating temperature range ?40c to +85c storage temperature range ?65c to +125c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 8-lead lfcsp 77 14 c/w maximum power dissipation the maximum safe power dissipation in the AD8128 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8128. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for the output. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. for each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the airflow increases heat dissipation, effectively reducing ja . also, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb surface, which is thermally connected to a copper plane to achieve the specified ja . figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead lfcsp (48.5c/w) on a jedec standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a pcb plane. extra thermal relief is required for operation at high supply voltages. 3.0 0 ?30?40 ?10?20 10 03 0 20 5040 7060 9080 110100 130120 05699-020 ambient temperature (c) maximum power dissip a tion (w) 2.5 2.0 1.5 1.0 0.5 figure 2. maximum power dissipation vs. temperature esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD8128 rev. 0 | page 5 of 12 pin configuration and fu nction descriptions pin 1 indicator 1v in+ 2v in? 3v gain 4 v peak 7v offset 8vs+ 6v out 5vs? top view (not to scale) AD8128 05699-002 figure 3. pin configuration table 4. pin function descriptions pin o. nemonic description 1 v in+ positive equalizer input 2 v in? negative equalizer input 3 v gain 0 v to 1 v broadband gain control 4 v peak 0 v to 1 v high frequency gain control 5 vs? negative power supply 6 v out equalizer output 7 v offset dc offset adjust 8 vs+ positive power supply ep gnd ground reference and thermal pad (see exposed pad (ep) section).
AD8128 rev. 0 | page 6 of 12 typical performance characteristics t a = 25c, v s = 5 v, r l = 150 , belden cable, v offset = 0 v, unless otherwise noted. 1.0 0 0 100 05699-003 cable length (m) optimized v peak and v gain (v) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 60 70 80 90 v out =2vp-p r l = 150 ? v peak v gain figure 4. v peak and v gain settings vs. cable length 10 20 30 ?70 05699-014 frequency (mhz) magnitude (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 0.1 1 10 100 1k 3k v peak =1v v peak =0.5v v peak =0v figure 5. frequency response for various v peak settings without cable 10 ?70 05699-013 frequency (mhz) magnitude (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 0.1 1 10 100 1k 3k v gain =1v v gain =0.5v v gain =0v figure 6. frequency response for various v gain settings without cable 2 ?10 0.1 05699-012 frequency (mhz) magnitude (db) 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 1 10 100 300 v peak and v gain settings are consistent with optimized settings in figure 4 v out =2vp-p r l = 150 ? figure 7. equalized frequenc y response for 50 m cable 2 ?10 0.1 05699-011 frequency (mhz) magnitude (db) 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 1 10 100 300 v peak and v gain settings are consistent with optimized settings in figure 4 v out =2vp-p r l = 150 ? figure 8. equalized frequenc y response for 100 m cable 1.5 ?1.5 0 200 05699-010 time (ns) output (v) 1.0 0.5 0 ?0.5 ?1.0 20 40 60 80 100 120 140 160 180 v peak and v gain settings are consistent with optimized settings in figure 4 figure 9. equalized pulse response for 50 m of cable
AD8128 rev. 0 | page 7 of 12 1.5 ?1.5 0 200 05699-009 time (ns) output (v) 1.0 0.5 0 ?0.5 ?1.0 20 40 60 80 100 120 140 160 180 v peak and v gain settings are consistent with optimized settings in figure 4 figure 10. equalized pulse response for 100 m of cable 40 ?40 ?4 4 05699-008 v in, cm (v) v out (mv) 30 20 10 0 ?10 ?20 ?30 ?3 ?2 ?1 0 1 2 3 figure 11. output voltage vs. common-mode input voltage 100 10 0.1 1k 05699-007 frequency (mhz) voltage noise (nv/ hz) 1 10 100 v peak =0v v gain =0v v peak =0.9v v gain = 0.225v figure 12. voltage noise vs. frequency 1.8 0 0 1.0 05699-006 v peak (v) integ r ated voltage noise from 100khz to 1ghz (mv) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 v gain settings are consistent with optimized settings in figure 4 figure 13. integrated voltage noise vs. v peak 6 ?6 0 500 05699-005 time (ns) voltage (v) 4 2 0 ?2 ?4 50 100 150 200 250 300 350 400 450 v peak =0v v gain =0v output input figure 14. overdriv e recovery time 20 ?80 0.1 1k 05699-004 frequency (mhz) common-mode rejection (db) 1 10 100 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 v gain =1v v peak =1v v gain =0v v peak =0v figure 15. common-mode rejection vs. frequency
AD8128 rev. 0 | page 8 of 12 10 ?70 0.001 1k 05699-015 frequency (mhz) powe r supply rejection (db) 0.01 0.1 1 10 100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?psr +psr v os =0v v peak =0v v gain =0v figure 16. power supply rejection vs. frequency test circuit v offset v offset v gain v gain v peak v peak v in+ v in? AD8128 hpf hpf lpf 05699-021 + + v s+ v s ? 1f 10f 10f 0.01f vs+ v s+ 1f 0.01f 0.01f 0.01f 0.01f vs? vs? 50 ? 50 ? cat-5 v out figure 17.
AD8128 rev. 0 | page 9 of 12 theory of operation the AD8128 is a high speed, low noise analog line equalizer that compensates for losses in cat-5/cat-5e cables up to 100 meters with 1 db flatness in the pass band out to 70 mhz (see figure 8 ). two continuously adjustable control voltages alter the frequency response to add flexibility to the system by allowing for the compensation of various cable lengths as well as for variations in the cable itself. the dc control voltage pin v gain adjusts ac broadband gain from 0 db to 3 db (see figure 6 ) to account for dc resistive losses present in the cable. a second dc control voltage pin v peak adjusts the amount of high frequency peaking (see figure 5 ) from 0 db to 20 db. this compensates for the high frequency loss due to the skin effect of the cable. the AD8128 has a high impedance differential input that allows it to receive dc-coupled signals directly from the cable. for systems with very high cmrr specifications, the AD8128 can also be used with a dedicated receiver, such as the ad8130 or ad8143, placed in front of it. the output of the AD8128 is low impedance and is capable of driving a 150 load resistor and up to 20 pf of load capacitance at its output. for systems with high parasitic capacitances at the output, it is recommended that a small series resistor be placed between the output and capacitive load to reduce ringing in the pulse response. the AD8128 is designed to be used in medium-length systems that have stringent low noise requirements as well as longer- length systems that can tolerate more noise. for the medium- length requirements, a single AD8128 is able to compensate up to 100 meters of cable with only 1.5 mv rms of output noise. for longer-length applications that require equalization of up to 200 meters of cable, two AD8128s can be cascaded together to achieve the desired equalization, while keeping approximately the same pass-band bandwidth, but with a slight degradation in settling time and slew rate. the frequency response of the AD8128 approximates the inverse frequency response of a lossy transmission line, which is given by () () fjkl efh + = 1 (1) where: f is the frequency. l is the length. k is the line constant. the AD8128 approximates the magnitude response of equation 1 by summing multiple zero-poles pairs offset at different frequencies. equalization adjustment due to varying line lengths is done by changing the weighting factors of each of the zero-pole pairs. input common-mode voltage range considerations when using the AD8128 as a receiver, it is important to ensure that the input common-mode (cm) voltage range of the AD8128 stays within the specified range. the input cm level can be easily calculated by adding the cm level of the driver, the amplitude of any sync pulses, and the other possible induced common-mode signals from power lines and fluorescent lights. v icm = v cm + v sync + v other (2) for example, when using a single 5 v supply on the drive side, the cm voltage of the line typically becomes the midsupply voltage, v cm = 2.5 v. furthermore, an addition of a sync signal, v sync = 0.5 v, on to the common mode puts the peak cm voltage at 3 v. assuming that both the driver and receiver have exactly the same ground potential, the signal is marginally below the upper end of the common-mode input range of 3.1 v. other cm signals that can be picked up by the cat-5 cable result in exceeding the cm input range of the AD8128. the most effective way of not exceeding the cm level of the AD8128 is to lower the cm level on the driver. in the previous example, this was the primary contributor to the cm input level. if this is not possible, a dedicated receiver with a wider cm input range, such as the ad8130 or ad8143, should be used.
AD8128 rev. 0 | page 10 of 12 applications kvm applications in kvm applications, cable equalization typically occurs at the root of the kvm network. in a star configuration, a driver is located at each of the end nodes and a receiver/equalizer is located at the single root node. in a daisy-chain configuration, each of the end nodes are connected to one another, and one of them is connected to the root. similarly, the drivers are placed on the nodes, and the receivers/equalizers are placed at the root. in both of these aforementioned configurations, three AD8128 receiver/equalizers can be used at the root node to equalize the transmitted red (r), green (g), and blue (b) channels for up to 100 meters of cable. since the skew between two pairs of cables in cat-5 is less than 1%, the control pins can be tied together and used as a single set of controls. if the common-mode levels of the inputs permit using the AD8128 as a receiver (see the input common-mode voltage range considerations section), the input signal should be terminated by a 100 shunt resistor between the pairs, or by two 50 shunt resistors with a common-mode tap in the middle. this cm tap can be used to extract the sync information from the signal if sync-on-common-mode is used. v offset v gain v peak v out v in+ v in? AD8128 hpf hpf lpf v cm 50? 50? v cm v diff v cm v diff cat-5 05699-016 figure 18. single receiver configuration for cat-5 equalizer dc control pins the AD8128 uses two control pins (v gain and v peak ) to adjust the equalization based on the length of the cable and one pin (v offset ) to adjust the dc output offset. v gain is a user-adjustable 0 v to 1 v broadband gain control pin, and v peak is a 0 v to 1 v adjustable high frequency gain pin to equalize for the skin effect in cat-5 cable. the values of both v peak and v gain are linearly correlated to the length of the cable to be equalized. a simple formula can be used to approximate the desired values for both of these pins. 425m/v )( mlength v gain (3) 110m/v )( mlength v peak (4) while these equations give a close approximation of the desired value for each pin, to achieve optimal performance, it may be necessary to adjust these values slightly. figure 19 and figure 20 illustrate circuits used to adjust the control pins on the AD8128. in figure 19 , a 1 k potentiometer is used to adjust the control pin voltage between the specified range of 0 v to 1 v. in figure 20 , a 2 k potentiometer is used to control the offset pin from ?2.5 v to +2.5 v. for both of these configurations, a 5v supply is assumed. control pin v gain or v peak 0.01f +5 v 4k ? 1k ? 0 5699-017 figure 19. circuit to control v gain and v peak (0 v to 1 v) offset 0.01f +5 v ?5v 1k ? 1k ? 2k ? 05699-018 figure 20. circuit to control v offset (2.5 v)
AD8128 rev. 0 | page 11 of 12 v offset v gain v peak v offset v gain v peak v out v in+ v in? AD8128 hpf hpf lpf v offset v gain v peak v out v in+ v in? AD8128 hpf hpf lpf 05699-019 + + vs+ v s? 1f 0.01f vs+ v s+ 1f 0.01f vs+ v s+ 1f 0.01f vs? vs? 1f 0.01f vs? vs? figure 21. cascaded AD8128 configuration cascaded applications to equalize distances longer than the specified 100 meters, the AD8128 can be cascaded to provide equalization for longer distances. when combining two AD8128s in series, it is possible to link the control pins together and use them like a single control pin for up to 200 meters of equalization. in this configuration, it is important to note that some key video specifications can be slightly degraded. by combining two equalizers in series, specifications such as rise time and settling time both increase while 3 db bandwidth decreases slightly. also, integrated noise is increased because the second equalizer adds gain. subjective testing should be done to determine the appropriate setting for the three control pins for optimum equalization. exposed pad (ep) the 8-lead lfcsp has an exposed paddle on the underside of its body. to achieve the specified thermal resistance, it must have a good thermal connection to one of the pcb planes. the exposed paddle must be soldered to a pad on top of the board connected to an inner plane with several thermal vias. for the AD8128, this pad must also be electrically connected to ground to provide a ground reference to the part. layout and power supply decoupling considerations standard high speed pcb layout practices should be adhered to when designing with the AD8128. a solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins and control pins. small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling. evaluation boards there are two evaluation boards available for easy characterization of the AD8128. a general-purpose evaluation board consisting of a single AD8128, with an option of also using a dedicated receiver, is available for simple characterization of the part. additionally, a kvm application specific evaluation board is available. this evaluation board consists of six AD8128s to equalize each of the rgb channels up to 200 meters, a 16-pin 26c32 comparator for sync-on-common-mode extract and a triple op amp to provide additional gain if necessary.
AD8128 rev. 0 | page 12 of 12 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 2.75 bsc sq top view 12 max 0.70 max 0.65 typ seating plane pin 1 indicator 0.90 max 0.85 nom 0.30 0.23 0.18 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.00 bsc sq 5 8 figure 22. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters ordering guide model temperature range package description package option branding AD8128acpz-r2 1 C40c to +85c 8-lead lead frame chip scale package (lfcsp_vd) cp-8-2 hzb AD8128acpz-rl 1 C40c to +85c 8-lead lead frame chip scale package (lfcsp_vd) cp-8-2 hzb AD8128acpz-r7 1 C40c to +85c 8-lead lead frame chip scale package (lfcsp_vd) cp-8-2 hzb 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05699-0-10/05(0)

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